Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.

The study of neuron interactions and hardware implementations are crucial research directions in neuroscience, particularly in developing large-scale biological neural networks. The FitzHugh-Nagumo (FHN) model is a popular neuron model with highly biological plausibility, but its complexity makes it difficult to apply at scale. This paper presents a cost-saving and improved precision approximation algorithm for the digital implementation of the FHN model. By converting the computational data into floating-point numbers, the original multiplication calculations are replaced by adding the floating-point exponent part and fitting the mantissa part with piecewise linear. In the hardware implementation, shifters and adders are used, greatly reducing resource overhead. Implementing FHN neurons by this approximation calculations on FPGA reduces the normalized root mean square error (RMSE) to 3.5% of the state-of-the-art (SOTA) while maintaining a performance overhead ratio improvement of 1.09 times. Compared to implementations based on approximate multipliers, the proposed method achieves a 20% reduction in error at the cost of a 2.8% increase in overhead.This model gained additional biological properties compared to LIF while reducing the deployment scale by only 9%. Furthermore, the hardware implementation of nine coupled circular networks with eight nodes and directional diffusion was carried out to demonstrate the algorithm's effectiveness on neural networks. The error decreased to 60% compared to the single neuron of the SOTA. This hardware-friendly algorithm allows for the low-cost implementation of high-precision hardware simulation, providing a novel perspective for studying large-scale, biologically plausible neural networks.

Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.

As a crucial component of neuromorphic chips, on-chip memory usually occupies most of the on-chip resources and limits the improvement of neuron density. The alternative of using off-chip memory may result in additional power consumption or even a bottleneck for off-chip data access. This article proposes an on- and off-chip co-design approach and a figure of merit (FOM) to achieve a trade-off between chip area, power consumption, and data access bandwidth. By evaluating the FOM of each design scheme, the scheme with the highest FOM (1.085× better than the baseline) is adopted to design a neuromorphic chip. Deep multiplexing and weight-sharing technologies are used to reduce on-chip resource overhead and data access pressure. A hybrid memory design method is proposed to optimize on- and off-chip memory distribution, which reduces on-chip storage pressure and total power consumption by 92.88% and 27.86%, respectively, while avoiding the explosion of off-chip access bandwidth. The co-designed neuromorphic chip with ten cores fabricated under standard 55 nm CMOS technology has an area of 4.4 mm 2 and a core neuron density of 4.92 K/mm 2, an improvement of 3.39  âˆ¼ 30.56× compared with previous works. After deploying a full-connected and a convolution-based spiking neural network (SNN) for ECG signal recognition, the neuromorphic chip achieves 92% and 95% accuracy, respectively. This work provides a new path for developing high-density and large-scale neuromorphic chips.

A Co-Designed Neuromorphic Chip With Compact (17.9K F2) and Weak Neuron Number-Dependent Neuron/Synapse Modules.

Many efforts have been made to improve the neuron integration efficiency on neuromorphic chips, such as using emerging memory devices and shrinking CMOS technology nodes. However, in the fully connected (FC) neuromorphic core, increasing the number of neurons will lead to a square increase in synapse & dendrite costs and a high-slope linear increase in soma costs, resulting in an explosive growth of core hardware costs. We propose a co-designed neuromorphic core (SRCcore) based on the quantized spiking neural network (SNN) technology and compact chip design methodology. The cost of the neuron/synapse module in SRCcore weakly depends on the neuron number, which effectively relieves the growth pressure of the core area caused by increasing the neuron number. In the proposed BICS chip based on SRCcore, although the neuron/synapse module implements 1∼16 times of neurons and 1∼66 times of synapses, it only costs an area of 1.79 × 107 F2, which is 7.9%∼38.6% of that in previous works. Based on the weight quantization strategy matched with SRCcore, quantized SNNs achieve 0.05%∼2.19% higher accuracy than previous works, thus supporting the design and application of SRCcore. Finally, a cross-modeling application is demonstrated based on the chip. We hope this work will accelerate the development of cortical-scale neuromorphic systems.